1. Field of the Invention
The present invention relates to a regulator circuit, and relates particularly to a regulator circuit that can quickly recover from the halted state to the operating state.
2. Description of the Related Art
In order to generate a desired internal voltage, a regulator circuit is mounted in a semiconductor integrated circuit. The regulator circuit is used, for example, when a power voltage required for the internal operation of a semiconductor integrated circuit is to be generated based on an externally input power voltage. Also, for a semiconductor memory device, the regulator circuit is employed when a predetermined voltage used for a reading or a writing operation is to be generated based on a voltage output by a charge pump circuit.
Currently, a demand exists for low power consumption semiconductor integrated circuits that can be mounted in portable devices, such as cellular phones. In use, when such a semiconductor integrated circuit enters a standby state, a regulator circuit mounted thereon should be halted to limit the consumption of power. And later, when the semiconductor integrated circuit recovers from the standby state to the active state, the regulator circuit must be able to recover quickly and supply predetermined voltages.
FIG. 9 is a diagram showing the arrangement of a conventional regulator circuit. A regulator circuit 100 includes a detection circuit 11, for detecting an output voltage VOUT and for generating and outputting a voltage (a feedback voltage) VFB consonant with the output voltage VOUT; an operational amplification circuit 12, for comparing the output voltage VFB of the detection circuit 11 with a reference voltage VREF and outputting a comparison result VAOUT; and an output circuit 13, for supplying a current to the output terminal, based on the output voltage VAOUT of the operational amplification circuit 12, to maintain the fixed output voltage VOUT.
The detection circuit 11 is a series circuit that includes resistors R0 and R1, which are connected between the output voltage VOUT terminal and the ground voltage terminal, and an N-channel transistor N0. The feedback voltage VFB is extracted at the juncture of the resistors R0 and R1, and the gate of the N-channel transistor N0 is connected to a contact for a control signal ENREG.
The feedback voltage VFB is applied to the non-inverted input terminal of the operational amplification circuit 12 and the reference voltage VREF is applied to the inversion input terminal, and the operational amplification circuit 12 is driven by a power source HV. Further, the control signal ENREG is transmitted to the operational amplification circuit 12.
The output circuit 13 is a P-channel transistor P0, and the gate is connected to the output terminal VAOUT of the operational amplification circuit 12, the source is connected to the power source HV, and the drain is connected to the output terminal VOUT. In accordance with the output voltage VAOUT of the operational amplification circuit 12, a current is supplied to the output terminal VOUT.
The control signal ENREG is a control signal for controlling the starting and the halting of the operation of the regulator circuit 100. When the control signal ENREG is at level H, the N-channel transistor N0 in the detection circuit 11 is set to the ON state, the operational amplification circuit 12 is activated, and the regulator circuit 100 is set to the operating state. When the control signal ENREG is at level L, the N-channel transistor N0 in the detection circuit 11 is set to the OFF state, the operational amplification circuit 12 is inactivated, and the regulator circuit 100 is halted. At this time, the power consumed by the regulator circuit 100 drops to zero.
A decoupling capacitor 30 and a load circuit 31 are connected to the output terminal VOUT of the regulator circuit 100. The decoupling capacitor 30 is additionally provided in order to suppress the fluctuation of the output voltage VOUT. The load circuit 31 is a destination to which the output voltage is supplied, and an actual load is represented as a model by using a current source IL and a switch SW.
Hereinafter, assume this is a case wherein the reference voltage VREF=1.25 V, the power voltage HV=5.4 V and the output voltage VOUT=4.6 V. These voltage values are employed for a case wherein the regulator circuit generates a voltage of 4.6 V to be applied to a word line during a reading operation for a flash memory. The power voltage HV=5.4 V is generated by raising the internal power voltage of 1.8 V using the charge pump circuit.
FIGS. 10A and 10B are diagrams showing waveforms for various operations performed for the conventional regulator circuit. As shown in FIG. 10A, when the control signal ENREG is at level H, the regulator circuit is active (the operating state), and when the current has been consumed by the load circuit 31 (the switch SW is at level H), it supplies a current and maintains the fixed output voltage VOUT.
When the control signal ENREG is at level L, the regulator circuit 100 is in the standby state (the halted state), and the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. When the load circuit 31 is to consume current while the regulator circuit is in the standby state, the control signal ENREG goes to level H and the regulator circuit recovers from the standby state to the active state and begins to supply a current to the load circuit 31.
As shown in FIG. 10B, the output voltage VOUT of the regulator circuit in the active state is 4.6V. Since a current is supplied to the load circuit 31 by the regulator circuit each time the current is consumed by the load circuit 31, the drop in the output voltage VOUT is a very small value, i.e., VD1, and the fixed value of the output voltage VOUT is maintained. At this time, the feedback voltage VFB, which is the input voltage for the operational amplification circuit 12, is a value (1.25 V) equal to the reference voltage VREF.
When at this time any current is not consumed by the load circuit 31, the control signal ENREG goes to level L and the regulator circuit is shifted to the standby state. At this time, the current consumed by the detection circuit 11 and the operational amplification circuit 12 is zero. Further, the power voltage HV is output by the output terminal VAOUT of the operational amplification circuit 12, and thus, the P-channel transistor P0 in the output circuit 13 is rendered OFF and the output terminal VOUT is set to a high impedance state.
As a result, the capacitance C of the decoupling capacitor 30 maintains the output voltage VOUT in the standby state at the voltage 4.6 V in the operating state. Since the N-channel transistor N0 in the detection circuit 11 is in the OFF state, the feedback voltage VFB is set so it is near the output voltage 4.6 V. When the load circuit 31 consumes current while the regulator circuit is in the standby state, the control signal ENREG goes to level H, and the regulator circuit recovers from the standby state to the active state and begins to supply a current to the load circuit 31 (see, for example, JP-A-2002-312043 and JP-A-2000-331479).
However, the conventional regulator circuit cannot quickly recover from the standby state to the active state. In the standby state, as shown in FIG. 10B, since the feedback voltage VFB is set so it is near the output voltage VOUT=4.6 V, a time T is required for the regulator circuit to recover from the standby state to the active state because, for a stable operation, the feedback voltage VFB is shifted from 4.6 V to VREF=1.25 V.
Since the load circuit 31 continuously consumes current during a period lasting until the regulator circuit is shifted to the stable operation state and begins to supply a current, there is a large voltage drop VD2 in the output voltage VOUT.
To prevent this voltage drop VD2, an increase in the value of the capacitance C of the decoupling capacitor 30 is considered. However, in this case, the chip area would be increased because a larger decoupling capacitor would be employed, and accordingly, the cost of the semiconductor integrated circuit would be increased.